1. Field of the Invention
The present invention generally relates to non-volatile semiconductor memory devices, and more particularly, the present invention relates to non-volatile semiconductor memory devices which include phase-change memory cells.
A claim of priority is made to Korean Patent Application No. 10-2005-0105964, filed Nov. 7, 2005, in the Korean Intellectual Property Office, the entirety of which is incorporated herein by reference.
2. Description of the Related Art
A phase-change random access memory (PRAM), also known as an Ovonic Unified Memory (OUM), includes a phase-change material such as a chalcogenide alloy which is responsive to energy (e.g., thermal energy) so as to be stably transformed between crystalline and amorphous states. Such a PRAM is disclosed, for example, in U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase-change material of the PRAM exhibits a relatively low resistance in its crystalline state, and a relatively high resistance in its amorphous state. In conventional nomenclature, the low-resistance crystalline state is referred to as a ‘set’ state and is designated logic “0”, while the high-resistance resistance amorphous state is referred to as a ‘reset’ state and is designated logic “1”.
The terms “crystalline” and “amorphous” are relative terms in the context of phase-change materials. That is, when a phase-change memory cell is said to be in its crystalline state, one skilled in the art will understand that the phase-change material of the cell has a more well-ordered crystalline structure when compared to its amorphous state. A phase-change memory cell in its crystalline state need not be fully crystalline, and a phase-change memory cell in its amorphous state need not be fully amorphous.
Generally, the phase-change material of a PRAM is reset to an amorphous state by joule heating of the material in excess of its melting point temperature for a relatively short period of time. On the other hand, the phase-change material is set to a crystalline state by heating the material below its melting point temperature for a longer period of time. In each case, the material is allowed to cool to its original temperature after the heat treatment. Generally, however, the cooling occurs much more rapidly when the phase-change material is reset to its amorphous state.
The speed and stability of the phase-change characteristics of the phase-change material are critical to the performance characteristics of the PRAM. As suggested above, chalcogenide alloys have been found to have suitable phase-change characteristics, and in particular, a compound including germanium (Ge), antimony (Sb) and tellurium (Te) (e.g., Ge2Sb2Te5 or GST) exhibits a stable and high speed transformation between amorphous and crystalline states.
FIGS. 1A and 1B illustrate a memory cell 10 in a ‘set’ state and in a ‘reset’ state, respectively. In this example, the memory cell 10 includes a phase-change resistive element 11 and a transistor 20 connected in series between a bit line BL and a reference potential (e.g., ground), with the transistor 20 being gated to a word line WL. It should be noted that FIGS. 1A and 1B are general schematic views only, that the configuration of the phase-change resistive element 11 is presented as an example only, and that other configurations and connections with respect to the phase-change resistive element 11 are possible. As an example of one variation, the phase-change resistive element 11 may instead be connected in series with a diode between the bit line BL and the word line WL.
In each of FIGS. 1A and 1B, the phase-change resistive element 11 includes a top electrode 12 formed on a phase-change material 14. In this example, the top electrode 12 is electrically connected to a bit line BL of a PRAM memory array (not shown). A conductive bottom electrode contact (BEC) 16 is formed between the phase-change material 14 and a conductive bottom electrode 18. The access transistor 20 is electrically connected between the bottom electrode 18 and the reference potential. As already suggested, the gate of the access transistor 20 is electrically connected to the word line WL of the PRAM cell array (not shown).
In FIG. 1A, the phase-change material 14 is illustrated as being in its crystalline state. As described previously, this means that the memory cell 10 is in a low-resistance ‘set’ state or logic 0 state. In FIG. 1B, a portion of the phase-change material 14 is illustrated as being amorphous. Again, this means that the memory cell 10 is in a high-resistance ‘reset’ state or logic 1 state.
The set and reset states of the memory cell 10 of FIGS. 1A and 1B are established by controlling the magnitude and duration of current flow through the BEC 16. That is, the phase-change resistive element 11 is activated (or accessed) by operation of the access transistor 20 which is responsive to a voltage of the word line WL. When activated, the memory cell 10 is programmed according to the voltage of the bit line BL. The bit line BL voltage is controlled to establish a programming current ICELL which causes the BEC 16 to act as a resistive heater which selectively programs the phase-change material 14 in its ‘set’ and ‘reset’ states.
FIG. 2 illustrates an example of temperature pulse characteristics of phase-change material as the phase-change material is programmed in the ‘set’ and ‘reset’ states. In particular, reference number 35 denotes the temperature pulse of the phase-change material programmed to its ‘reset’ state, and reference number 36 denotes the temperature pulse of the phase-change material programmed to its ‘set’ state.
As shown in FIG. 2, when the phase-change material is programmed to its ‘reset’ state, the temperature of the material is increased above its melting temperature Tm (e.g., 610° C.) for a relatively short period of time, and then allowed to rapidly cool. In contrast, when the phase-change material is programmed to its ‘set’ state, the temperature of the material is increased to below its melting point Tm and above its crystallizing temperature Tx (e.g., 450° C.) for a longer period of time, and then allowed to cool more slowly. The fast and slow cooling of the ‘reset’ and ‘set’ programming operations are referred to in the art as fast “quenching” and slow “quenching”, respectively. The temperature range between the melting temperature Tm and the crystallizing temperature Tx is referred to as the “set window”.
FIG. 3 is a graph illustrating the resistive characteristic (current versus voltage) of a phase-change material for each of its ‘set’ and ‘reset’ states. In particular, line 46 is representative of the resistive characteristic of a phase-change material in its ‘set’ state, and line 45 is representative of the same in its ‘reset’ state. As shown, the set and reset resistances differ substantially below a threshold voltage (e.g., 1v), but become substantially equal to one another above the threshold voltage. In order to maintain the necessary sensing margin during reading operations, it is necessary to restrict the bit line BL voltage to a region below the voltage threshold. As explained below with reference to FIG. 4, a clamping transistor inserted in the bit line BL may be used for this purpose.
FIG. 4 is a simplified circuit diagram for explaining write and read operations of the phase-change memory cell. As shown, a bit line BL is coupled to a write driver 24 and a read circuit 26. Also connected to the bit line BL are a phase-change memory cell 10, a pre-charge transistor 20, and a select transistor 22.
In this example, the phase-change memory cell 10 includes a phase-change element and transistor connected in series between the bit line BL and a reference potential (e.g., ground), where the transistor is gated to a word line WL. As suggested previously, other configurations of the phase-change memory cell 10 are possible. For example, the phase-change memory cell 10 may instead include a phase-change memory element and diode connected between the bit line BL and word line WL.
As those skilled in the art will appreciate, the precharge transistor 20 (gated to a precharge control signal PREBL) is used to precharge the bit line BL in a read and/or write operation, while the select transistor 22 (gated to a y-address signal YSEL) is used to activate the bit line BL.
The write driver 24 typically includes a current mirror 28 for applying either a reset current RESET or a set current SET as a write current iwrite to the bit line BL during a write operation. The reset current RESET and the set current SET were discussed previously in connection with FIG. 2.
The read circuit 26 is functional in a read operation to apply a read current iread from a current source READ to the bit line BL. A clamping transistor 30, which is gated to a clamp control signal VCLAMP, restricts the bit line BL voltage to a region below the voltage threshold discussed above in connection with FIG. 3. A sense-amplifier S/A compares the voltage of the bit line BL with a reference voltage VREF, and outputs the comparison result as output data OUT.
As with other types of non-volatile memory devices, efforts are being made to reduce the level of the supply voltages utilized to drive phase-change memory devices. However, any reduction in supply voltage levels can adversely impact the sensing margins in the read operation discussed operation.